Reducing write latencies for shared data in a multiprocessor with a multistage network

Performance of cache coherence protocols can be severely restricted by the consistency model of the architecture. If a packet-switched, cyclic network is used, such as a multistage network, pipelining may violate strict consistency models such as sequential consistency. The paper shows that by meeting a few constraints in the implementation of the cache coherence protocol, store requests can be pipelined. The new requirements are applied to a previously proposed cache coherence protocol for a MIN-based network. The most important constraints are: to augment the protocol with the notion of write-permission; avoiding redundant paths between any two caches, and the use of a distributed cache coherence protocol. It is shown how the ideas can be generalized to a wide class of cache coherence protocols