DocumentCode
2789207
Title
Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path
Author
Galanis, Michalis D. ; Dimitroulakos, Gregory ; Goutis, Costas E.
Author_Institution
Dept. of Electr. & Comput. Eng., Patras Univ.
fYear
2007
fDate
26-30 March 2007
Firstpage
1
Lastpage
8
Abstract
This paper presents the performance improvements and the energy reductions by coupling a high-performance coarse-grained reconfigurable data-path with a microprocessor in a generic platform. The datapath has been previously introduced by the authors. It is composed by computational units able to realize complex operations which aid in improving the performance of time critical application parts, called kernels. A design flow is proposed for mapping high-level software descriptions to the microprocessor system. Eight real-life applications are mapped on three different instances of the system. Significant overall application speedups, relative to a software-only solution, ranging from 1.74 to 3.94 are reported being close to theoretical speedup bounds. Average energy savings of 59% are achieved, while the reduction in the system energy-delay product ranges from 66% to 92%.
Keywords
field programmable gate arrays; logic design; microprocessor chips; reconfigurable architectures; coarse-grained reconfigurable data-path; complex arithmetic structures; field programmable gate arrays; single-chip microprocessor system; Application software; Delay; Energy consumption; Field programmable gate arrays; Hardware; Kernel; Microprocessors; Parallel processing; Programmable logic arrays; Reconfigurable logic;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International
Conference_Location
Long Beach, CA
Print_ISBN
1-4244-0910-1
Electronic_ISBN
1-4244-0910-1
Type
conf
DOI
10.1109/IPDPS.2007.370383
Filename
4228111
Link To Document