• DocumentCode
    2791031
  • Title

    Simulation coverage enhancement using test stimulus transformation

  • Author

    Ip, C.N.

  • Author_Institution
    Cadence Berkeley Labs., CA, USA
  • fYear
    2000
  • fDate
    5-9 Nov. 2000
  • Firstpage
    127
  • Lastpage
    133
  • Abstract
    This paper introduces the concept of abstract state exploration histories to a simulation environment, and presents a test stimulus transformation (TST) technique to improve simulation coverage. State exploration histories are adapted from reachability analysis in Formal Verification. In TST, an aggressively abstracted state exploration history is maintained during simulation. While this history is being collected, test stimuli from an existing test bench are transformed on-the-fly to explore new scenarios that are not in the history. The results showed that 3-fold increase in transition coverage for a cache coherence controller, and 10 times faster coverage convergence for a MPEG2 decoder can be achieved.
  • Keywords
    formal verification; logic simulation; logic testing; reachability analysis; Formal Verification; MPEG2 decoder; abstract state exploration; cache coherence controller; reachability analysis; simulation environment; state exploration histories; test stimulus transformation; Concrete; Convergence; Decoding; Formal verification; History; Logic design; Performance evaluation; Reachability analysis; Technological innovation; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1092-3152
  • Print_ISBN
    0-7803-6445-7
  • Type

    conf

  • DOI
    10.1109/ICCAD.2000.896462
  • Filename
    896462