Title :
A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2–;10 Gb/s ADC-based receivers
Author :
Tahmoureszadeh, Tina ; Sarvari, Siamak ; Sheikholeslami, Ali ; Tamura, Hirotaka ; Tomita, Yasumoto ; Kibune, Masaya
Author_Institution :
Dept. of Elec. & Comp. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
This paper presents a combined anti-aliasing filter and 2-tap feed-forward equalizer (AAF/FFE) as an analog front-end (AFE) for 2× blind ADC-based receivers. The front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The AAF bandwidth scales with the data-rate and the 2-tap FFE is designed without the need for noise-sensitive analog delay cells. The AAF/FFE is implemented in 65-nm CMOS, occupies 0.013 mm2, and consumes 2.4 mW at 10 Gb/s.
Keywords :
CMOS integrated circuits; analogue-digital conversion; blind equalisers; delay filters; 2-tap feed-forward equalizer; CMOS integrated circuits; analog front-end; anti-aliasing filter; bit rate 2 Gbit/s to 10 Gbit/s; blind ADC-based receivers; channel/filter characteristics; power 2.4 mW; size 65 nm; CMOS integrated circuits; Clocks; Conferences; Frequency measurement; Frequency response; Jitter; Receivers;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617602
