Title :
Potential slack: an effective metric of combinational circuit performance
Author :
Chunhong Chen ; Xiaojian Yang ; Sarrafzadeh, M.
Author_Institution :
Dept. of Electr. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
Abstract :
This paper proposes the concept of potential slack and shows that it is an effective metric of combinational circuit performance. We provide several methods for estimating potential slack and prove one (a maximal-independent-set based algorithm) in particular which works best. Experiments in gate sizing show that potential slack provides 100% correct prediction for circuit area optimization. We also explore the role of potential slack in timing-driven placement.
Keywords :
circuit CAD; combinational circuits; timing; circuit area optimization; combinational circuit performance; gate sizing; potential slack; timing-driven placement; Combinational circuits; Cost function; Degradation; Delay effects; Design optimization; Logic circuits; Power dissipation; Timing; Upper bound; Wiring;
Conference_Titel :
Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-6445-7
DOI :
10.1109/ICCAD.2000.896474
