DocumentCode
2791256
Title
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
Author
Becerra, Yolanda ; Beltran, Vicenç ; Carrera, David ; González, Marc ; Torres, Jordi ; Ayguadé, Eduard
Author_Institution
Barcelona Supercomput. Center (BSC), Tech. Univ. of Catalonia (UPC), Barcelona, Spain
fYear
2009
fDate
22-25 Sept. 2009
Firstpage
42
Lastpage
49
Abstract
In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system architectures, operating systems and networks. Exploiting the intrinsic multi-level parallelism present in such a complex execution environment has become a challenging task using traditional parallel and distributed programming models. As a result, an increasing need for novel approaches to exploiting parallelism has arisen in these environments. MapReduce is a data-driven programming model originally proposed by Google back in 2004 as a flexible alternative to the existing models, specially devoted to hiding the complexity of both developing and running massively distributed applications in large compute clusters. In some recent works, the MapReduce model has been also used to exploit parallelism in other non-distributed environments, such as multi-cores, heterogeneous processors and GPUs. In this paper we introduce a novel approach for exploiting the heterogeneity of a Cell BE cluster linking an existing MapReduce runtime implementation for distributed clusters and one runtime to exploit the parallelism of the Cell BE nodes. The novel contribution of this work is the design and evaluation of a MapReduce execution environment that effectively exploits the parallelism existing at both the Cell BE cluster level and the heterogeneous processors level.
Keywords
microcomputers; parallel programming; Cell BE cluster; MapReduce applications; data driven programming model; distributed programming model; graphics processing unit; hardware accelerators; heterogeneous processors; intrinsic multilevel parallelism; multicores processor; parallel programming model; Acceleration; Computer applications; Computer architecture; Computer networks; Costs; Hardware; Operating systems; Parallel processing; Parallel programming; Runtime; Hardware Accelerators; MapReduce; cell BE; multi-core processors;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing, 2009. ICPP '09. International Conference on
Conference_Location
Vienna
ISSN
0190-3918
Print_ISBN
978-1-4244-4961-3
Electronic_ISBN
0190-3918
Type
conf
DOI
10.1109/ICPP.2009.59
Filename
5361805
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