Title :
Data path placement with regularity
Author :
Tao Ye, T. ; De Micheli, G.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
As more data processing functions are integrated into systems-on-chip, data path is becoming a critical part of the whole VLSI design. However, traditional physical design methodology can not satisfy the data path performance requirement because it has no knowledge of the data path bit-sliced structure. In this paper, an Abstract Physical Model (APM) is proposed to extract bit-slice regularity information from Data Flow Graph (DFG) and it is used for interconnect and congestion planning. A two step heuristic algorithm is introduced to optimize the linear placement of APM to satisfy both the wire length and routing track budget.
Keywords :
circuit layout CAD; data flow graphs; Abstract Physical Model; Data Flow Graph; bit-slice regularity; congestion planning; data path; data path placement; interconnect; routing track; systems-on-chip; wire length; Application specific integrated circuits; Circuit synthesis; Data mining; Delay estimation; Integrated circuit interconnections; Routing; Signal synthesis; Timing; Very large scale integration; Wire;
Conference_Titel :
Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-6445-7
DOI :
10.1109/ICCAD.2000.896484
