A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC

Author

Lin, David T. ; Li, Li ; Farahani, Shahin ; Flynn, Michael P.

Author_Institution

Univ. of Michigan, Ann Arbor, MI, USA

fYear

2010

fDate

19-22 Sept. 2010

Firstpage

1

Lastpage

4

Abstract

A flexible, digital-dominant wireless receiver in implemented in 65nm CMOS. The receive chain consists of a wide-band LNA, mixers, and baseband amplifiers. A 7b 21MS/s SAR ADC with embedded, configurable DT FIR/IIR filtering rejects aliasing interferers. Interleaving of sampling and SAR in the ADC maximizes conversion rate. The receiver achieves -92 dBm sensitivity, +33dB and +39dB adjacent and alternate channel interferer rejection with 802.15.4 packets, respectively, and -83dBm sensitivity, +41dB, +20MHz interferer rejection with 802.11 packets.

Keywords

CMOS integrated circuits; FIR filters; IIR filters; analogue-digital conversion; low noise amplifiers; mixers (circuits); radio receivers; CMOS; SAR ADC; baseband amplifiers; configurable DT FIR filter; configurable DT FIR/IIR filtering; flexible digital-dominant wireless receiver; frequency 500 MHz to 3.6 GHz; mixers; size 65 nm; wideband LNA; Finite impulse response filter; Frequency measurement; IEEE 802.11 Standards; IIR filters; Receivers; Sensitivity;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4244-5758-8

Type

conf

DOI

10.1109/CICC.2010.5617620

Filename

5617620