An optimized phased-array antenna for intra-chip communications

The continued migration to smaller nanometer geometries brought fundamental limits to traditional on-chip hard wires performance. According to the International Technology Roadmap for Semiconductor (ITRS), feature size shrinking leads an increase in the operating frequency of RFCMOS devices. Thus, new interconnect methodologies such as radio frequency (RF) wireless can be employed on future chips projected for intra-chip wireless data communications. The size of Si integrated antenna in these frequencies will be several millimetres and the antenna length will be decrease by frequency increasing. In this paper, we have proposed an optimum radiation pattern achieved by a phased array (PA) antenna for wireless Network-on-Chip applications. We compare our PA characteristics to basic linear dipole antenna. Using CST Microwave Studio for simulation, a high transmission gain of -37.4 dB at 20 GHz is achievable from the pair of PA antennas at a separation of 6.25 mm on a high resistive silicon substrate which is at least 20 dB better than the dipole pair.