A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns

Author

Jacunski, Mark ; Anand, Darren ; Busch, Robert ; Fifield, John ; Lanahan, Matthew ; Lane, Paul ; Paparelli, Adrian ; Pomichter, Gary ; Pontius, Dale ; Roberge, Michael ; Sliva, Stephen

Author_Institution

IBM Syst. & Technol. Group, Essex Junction, VT, USA

fYear

2010

fDate

19-22 Sept. 2010

Firstpage

1

Lastpage

4

Abstract

A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for V_DD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank modes up to 1.67GHz for V_DD = 1.0V and nominal process. The staggered - folded BL architecture with BL twisting over both the array and SAs is described as well as a novel wordline timer which generates a 75% duty cycle signal from a 50% duty cycle clock.

Keywords

DRAM chips; embedded systems; random processes; silicon-on-insulator; BL twisting; SOI compiled embedded DRAM; SOI technology; duty cycle clock; duty cycle signal; eDRAM; frequency 1.67 GHz; multibank modes; random cycle times; size 45 nm; staggered-folded BL architecture; wordline timer; Arrays; Capacitance; Capacitors; Clocks; Random access memory; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4244-5758-8

Type

conf

DOI

10.1109/CICC.2010.5617634

Filename

5617634