Layout-driven area-constrained timing optimization by net buffering

With the advent of deep sub-micron technologies, interconnect loads and delays are becoming significant, and layout-driven synthesis has become the need of the day. However, given the tight constraints imposed by the layout (e.g., area availability, congestion), only those synthesis transforms can be made layout-driven that are local and layout-friendly. Examples of such transforms are net buffering, gate resizing, and gate replication. In this paper, we address the problem of minimizing the delay of a mapped, roughly placed, and globally-routed design by buffer insertion and/or deletion without violating the local area constraints imposed by the layout and without overloading any buffer/cell pins. We believe that this is one of the most fundamental problems in layout-driven buffer optimization. To the best of our knowledge, no technique has been established to date that solves this problem. The concept of local (or block) area constraints we use in this paper is more powerful than that of the total design area traditionally used in logic synthesis.