Low Power, High-Speed Radiation Hardened Computer & Flight Experiment

An architecture of a radiation tolerant, high speed, low power, low cost computer built from commercial-off-the-shelf (COTS) parts is presented. We discuss the underlying radiation mitigation technologies used, and demonstrate their (radiation-tolerance) capabilities by citing the radiation test results. Hardness against single event upsets (SEU) for COTS microprocessors is achieved using Time-Triple Modular Redundancytrade(TTMR). Single event functional interrupts (SEFI)(Koga et al., 1997) of the microprocessors are being mitigated with an auxiliary Hardened Coretrade(H-Core) chip. The other on-board chips used are a combination of space qualified, radiation hardened COTS parts. A flight unit of the computer based on the above mentioned technologies, Proton 100k, was adapted for the Air Force Research Laboratory´s Space Vehicles Directorate RoadRunner satellite program