Title :
Low Power, High-Speed Radiation Hardened Computer & Flight Experiment
Author :
Czajkowski, D.R. ; Pagey, M.P. ; Samudrala, P.K. ; Goksel, M. ; Viehman, M.J.
Author_Institution :
Space Micro, Inc., San Diego, CO
Abstract :
An architecture of a radiation tolerant, high speed, low power, low cost computer built from commercial-off-the-shelf (COTS) parts is presented. We discuss the underlying radiation mitigation technologies used, and demonstrate their (radiation-tolerance) capabilities by citing the radiation test results. Hardness against single event upsets (SEU) for COTS microprocessors is achieved using Time-Triple Modular Redundancytrade(TTMR). Single event functional interrupts (SEFI)(Koga et al., 1997) of the microprocessors are being mitigated with an auxiliary Hardened Coretrade(H-Core) chip. The other on-board chips used are a combination of space qualified, radiation hardened COTS parts. A flight unit of the computer based on the above mentioned technologies, Proton 100k, was adapted for the Air Force Research Laboratory´s Space Vehicles Directorate RoadRunner satellite program
Keywords :
low-power electronics; microprocessor chips; radiation hardening (electronics); space vehicle electronics; COTS microprocessors; Hardened Core chip; Proton 100k; Space Vehicles Directorate RoadRunner satellite program; Time-Triple Modular Redundancy; flight experiment; on-board chips; radiation hardened computer; radiation mitigation technologies; radiation tolerant; single event functional interrupts; single event upsets; Computer architecture; Costs; Laboratories; Microprocessors; Military computing; Protons; Radiation hardening; Single event upset; Space technology; Testing; FPGA; H-Core; Microprocessor; Radiation Tolerant; SEE; SEFI; SEU; TMR; TTMR;
Conference_Titel :
Aerospace Conference, 2005 IEEE
Conference_Location :
Big Sky, MT
Print_ISBN :
0-7803-8870-4
DOI :
10.1109/AERO.2005.1559559
