A RadHard-by-Design Clock Generator

Author

Hafer, Craig ; Schnathorst, Vern ; Pfeil, John ; Meade, Tim

Author_Institution

Aeroflex Colorado Springs

fYear

2005

fDate

5-12 March 2005

Firstpage

1

Lastpage

7

Abstract

Aeroflex Colorado Springs has designed and tested a RadHard-by-Design frequency and skew selectable clock generator integrated circuit (IC). The clock generator is implemented with a RadHard phase locked loop (PLL) and selectable skew control. The PLL is designed for low jitter performance in space applications. The RadHard clock generator achieves either 300 krad(Si) or greater than 1.0 Mrad(Si) total ionizing dose performance on a commercial 0.25mum shallow trench isolation CMOS line using RadHard-by-Design practices. Single event latchup (SEL), single event upset (SEU) and single event transient (SET), due to charged particle strikes, are mitigated by a combination of circuit and layout design techniques. The clock generator is SEL immune to > 109 MeV-cm⁶/mg

Keywords

CMOS integrated circuits; clocks; integrated circuit layout; isolation technology; phase locked loops; radiation hardening (electronics); 0.25 micron; RadHard clock generator; RadHard phase locked loop; circuit layout design techniques; clock generator integrated circuit; frequency selectable clock generator; selectable skew control; shallow trench isolation CMOS line; single event latchup; single event transient; single event upset; skew selectable clock generator; Circuit testing; Clocks; Frequency; Immune system; Integrated circuit testing; Jitter; Oscillators; Phase locked loops; Single event upset; Springs;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace Conference, 2005 IEEE

Conference_Location

Big Sky, MT

Print_ISBN

0-7803-8870-4

Type

conf

DOI

10.1109/AERO.2005.1559567

Filename

1559567