DocumentCode
2792721
Title
Models of multiprocessor computing
Author
Lenoski, Daniel E.
Author_Institution
Div. of Adv. Syst., Silicon Graphics Comput. Syst., Mountain View, CA, USA
fYear
1997
fDate
22-24 Oct 1997
Firstpage
28
Abstract
Today´s options for high-performance computing include message-passing MPP systems, clusters of workstations, shared-memory multiprocessors, and parallel vector processors. Shared-memory multiprocessors provide the most general-purpose programming model, but generally suffer from limited scalability. New multiprocessor cache coherence protocols together with high-performance CMOS VLSI and interconnects are enabling a new class of machine that scales the shared-memory paradigm. The author introduces the scalable shared-memory multiprocessor (SSMP) and SGI´s new Origin servers based on this technology. The Origin machines are highly modular and permit a single system to grow from a cost-effective deskside uniprocessor to a supercomputer with hundreds of processors and hundreds of gigabytes of shared-memory. Nodes within the system provide a peak of 50 GB/sec of memory bandwidth and are connected by fat hypercube network that has a peak bisection bandwidth of 25 GB/sec. These capabilities also enable new levels of I/O performance including file servers with sustained bandwidths in excess of 500 MByte/sec and networking interfaces such as SuperHIPPI that can source and sink data at up to 800 MB/sec simultaneously. He concludes the talk with a look at the future of multiprocessing. He predicts a merger of the HPC computing models on SSMP and clusters of SSMP systems
Keywords
VLSI; file servers; network interfaces; protocols; reconfigurable architectures; shared memory systems; 25 GB/s; 50 GB/s; 500 MByte/s; 800 MB/s; I/O performance; SGI Origin servers; SuperHIPPI; fat hypercube network; file servers; general-purpose programming model; high-performance CMOS VLSI; high-performance computing; interconnects; memory bandwidth; message-passing MPP systems; modular Origin machines; multiprocessor cache coherence protocols; multiprocessor computing models; networking interfaces; parallel vector processors; peak bisection bandwidth; scalable shared-memory multiprocessor; shared-memory multiprocessors; supercomputer; sustained bandwidths; workstation clusters; Bandwidth; CMOS technology; Coherence; Concurrent computing; Protocols; Scalability; Semiconductor device modeling; Vector processors; Very large scale integration; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Architecture for Future Generation High-Performance Processors and Systems, 1997
Conference_Location
Maui, HI
ISSN
1537-3223
Print_ISBN
0-8186-8424-0
Type
conf
DOI
10.1109/IWIA.1997.670403
Filename
670403
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