Analysis of latch-up in GaAs complementary logic structures

GaAs complementary FET logic structures have n⁺ and p ⁺ doped areas separated by areas of semi-insulating (SI) GaAs. Such doped patterns form stray p-i-n double injection diodes which may cause latch-up. Using a SPICE equivalent circuit for the latch-up diodes, the effect of latch-up on the performance of the logic gates has been simulated. This study shows that latch-up can severely affect the performance of the logic gates, and that the distance between the injecting contacts, background concentration of the SI material, and temperature are critical parameters in latch-up susceptibility