Abstract :
Linear feedback shift registers (LFSRs) have always received considerable attention in computer science especially in coding theory and in cryptography. The scope of applications of LFSRs is wide: data scrambling, spread spectrum, build in self tests (BISTs). They have to be implemented either in hardware or in software. Unlike hardware, software applications have not been very popular. The main reason is that, even if the LFSR synthesis in software is very similar to the LFSR synthesis on Xilinx FPGA, the overall processing is parallel in hardware while it is almost sequential in software, leading to low throughput implementations. If the naive LFSR implementation is in favor of hardware, increasing the number of LFSR steps computed at the same time can considerably improve software implementation. For instance, we obtain a 103 speedup factor for a 128-bit LFSR on 64-bit processors. Unfortunately, this cannot be obtain for all LFSRs. We here describe how LFSR parameters must be chosen to obtain an efficient implementation.
Keywords :
built-in self test; cryptography; encoding; field programmable gate arrays; shift registers; 103 speedup factor; 128-bit LFSR synthesis; 64-bit processor; Xilinx FPGA; build in self tests; coding theory; cryptography; data scrambling; linear feedback shift register; spread spectrum; Application software; Automatic testing; Codes; Computer science; Cryptography; Field programmable gate arrays; Hardware; Linear feedback shift registers; Spread spectrum communication; Throughput;
