Title :
Self-aligned and shielded-RESURF LDMOS for dense 20 V power IC´s
Author :
Ludikhuize, Adriaan W.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
A self-aligned 20 V logic-level n-channel LDMOS has been integrated in a 0.6 μm BiCMOS process, using a LATID (large angle tilted implementation drain) boron backgate implantation combined with co-implanted arsenic as a low-ohmic link under the spacer. In addition, a shielded RESURF LDMOS is reported for use as a low-side transistor in power converters, suited for 20 V in VLSI with a single thin gate oxide. This transistor suppresses parasitic injection in the substrate and uses a buried p on buried n+ layer
Keywords :
BiCMOS integrated circuits; VLSI; buried layers; dielectric thin films; ion implantation; power MOSFET; power convertors; power integrated circuits; 0.6 micron; 20 V; BiCMOS process; LATID boron backgate implantation; Si:B,As; VLSI; buried p on buried n+ layer; co-implanted arsenic; large angle tilted implementation drain boron backgate implantation; low-side transistor; power converters; self-aligned LDMOSFET; self-aligned logic-level n-channel LDMOS; shielded-RESURF LDMOSFET; single thin gate oxide layer; sub-spacer low-ohmic link; substrate parasitic injection suppression; Bridge circuits; Current measurement; Electrons; Epitaxial layers; Hot carriers; Implants; Motor drives; Semiconductor optical amplifiers; Substrates; Very large scale integration;
Conference_Titel :
Power Semiconductor Devices and ICs, 1999. ISPSD '99. Proceedings., The 11th International Symposium on
Conference_Location :
Toronto, Ont.
Print_ISBN :
0-7803-5290-4
DOI :
10.1109/ISPSD.1999.764060
