Title :
Low on-resistance lateral U-gate MOSFET with DSS pattern layout
Author :
Shimoida, Y. ; Hayami, Yasuaki ; Ohta, Katsumi ; Hoshi, Masakatsu ; Shinohara, Toshiro
Author_Institution :
Electron. & Inf. Syst. Res. Lab., Nissan Motor Co. Ltd., Yokosuka, Japan
Abstract :
This paper describes a low on-resistance lateral U-gate MOSFET having a DSS (drain window surrounded by source windows) pattern layout with TDRs (trench drain rings). The DSS pattern layout is effective in increasing the source cell density (Hoshi et al, 1995). The TDRs, which are filled with highly N+ doped polysilicon, shrink the drain cell size and reduce the resistance of the sinkers. Specific on-resistance of 0.38 mΩ·cm2 with a blocking voltage of 44 V is obtained
Keywords :
electric resistance; isolation technology; power MOSFET; semiconductor device measurement; 44 V; DSS pattern layout; Si; TDRs; blocking voltage; drain cell size; drain window surrounded by source windows pattern layout; highly N+ doped polysilicon filled TDRs; lateral U-gate MOSFET; on-resistance; sinker resistance; source cell density; specific on-resistance; trench drain rings; Automotive electronics; Decision support systems; Electrodes; FETs; Fabrication; Intelligent vehicles; Laboratories; MOSFET circuits; Power MOSFET; Voltage;
Conference_Titel :
Power Semiconductor Devices and ICs, 1999. ISPSD '99. Proceedings., The 11th International Symposium on
Conference_Location :
Toronto, Ont.
Print_ISBN :
0-7803-5290-4
DOI :
10.1109/ISPSD.1999.764097
