• DocumentCode
    2793835
  • Title

    UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design

  • Author

    Di Guglielm, L. ; Fummi, Franco ; Pravadelli, Graziano ; Stefanni, Francesco ; Vinco, Sara

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Verona, Verona, Italy
  • fYear
    2011
  • fDate
    9-11 Nov. 2011
  • Firstpage
    33
  • Lastpage
    40
  • Abstract
    Modern embedded systems require a tight integration among several heterogeneous components including both digital and analog HW, as well as HW-dependent SW. Moreover, they have a strict interaction with the surrounding physical environment. Traditional approaches for modeling such systems rely either on homogeneous top-down methodologies or on co-simulation frameworks. The former are generally based on a single model of computation. Thus, they do not easily allow to integrate existing components built by using different formalisms. The latter assemble heterogeneous components without providing a rigorous formal support, thus making integration and validation a very hard tasks. This paper proposes UNIVERCM, a formal computational model that allows to represent with a uniform syntax and a precise semantics heterogeneous systems composed of SW, analog and digital HW, as well as the environment they are embedded in. UNIVERCM is not intended to be explicitly used to describe a system, but rather to automatically convert into a uniform representation different descriptions written by using heterogeneous modeling languages.
  • Keywords
    embedded systems; formal verification; hardware-software codesign; simulation languages; HW-dependent SW; UNIVERCM; analog HW; cosimulation frameworks; digital HW; formal computational model; heterogeneous components; heterogeneous embedded system design; heterogeneous modeling languages; homogeneous top-down methodologies; semantic heterogeneous systems; syntax; universal versatile computational model; Apertures; Automata; Delay; Semantics; Synchronization; Syntactics; Valves;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Level Design Validation and Test Workshop (HLDVT), 2011 IEEE International
  • Conference_Location
    Napa Valley, CA
  • ISSN
    1552-6674
  • Print_ISBN
    978-1-4577-1744-4
  • Type

    conf

  • DOI
    10.1109/HLDVT.2011.6114163
  • Filename
    6114163