High-performance 13-65 V rated LDMOS transistors in an advanced smart power technology

Author

Merchant, S. ; Baird, R. ; Chang, S. ; Hui, P. ; Macary, V. ; Neaves, M.G.

Author_Institution

Motorola SPS Transp. Syst. Group, Mesa, AZ, USA

fYear

1999

fDate

1999

Firstpage

225

Lastpage

228

Abstract

A high-performance, low cost smart power technology targeting automotive applications in the 13-65 V range is described. The trade-off between on-state specific resistance and off-state breakdown voltage is detailed for four lateral double-diffused MOS structures. The characterization includes the effects of gate length and drift length, and scaling issues related to interconnect metal debiasing. Results compare favorably with competing technologies of higher cost and complexity

Keywords

MOS integrated circuits; automotive electronics; electric resistance; integrated circuit interconnections; integrated circuit metallisation; power MOSFET; power integrated circuits; semiconductor device breakdown; 13 to 65 V; LDMOS transistors; automotive applications; drift length; gate length; interconnect metal debiasing; lateral double-diffused MOS structures; off-state breakdown voltage; on-state specific resistance; scaling; smart power technology; voltage rating; Automotive engineering; Breakdown voltage; Costs; Fuels; Integrated circuit interconnections; Integrated circuit technology; Power integrated circuits; Transistors; Transportation; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1999. ISPSD '99. Proceedings., The 11th International Symposium on

Conference_Location

Toronto, Ont.

ISSN

1063-6854

Print_ISBN

0-7803-5290-4

Type

conf

DOI

10.1109/ISPSD.1999.764104

Filename

764104