• DocumentCode
    2793978
  • Title

    Analog transaction level modeling

  • Author

    Rath, Alexander W. ; Esen, Volkan ; Ecker, Wolfgang

  • Author_Institution
    Infineon Technol. AG, Neubiberg, Germany
  • fYear
    2011
  • fDate
    9-11 Nov. 2011
  • Firstpage
    82
  • Lastpage
    82
  • Abstract
    In this paper, we present a new abstraction technique that extends the existing verification methodologies OVM [2] and UVM to the analog domain. This abstraction technique is referred to as Analog Transaction Level Modeling.
  • Keywords
    analogue integrated circuits; integrated circuit design; integrated circuit modelling; OVM; UVM; abstraction technique; analog domain; analog transaction level modeling; universal verification methodology; verification methodologies; Buildings; Data models; Design methodology; Electronic mail; Integrated circuit modeling; Time frequency analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Level Design Validation and Test Workshop (HLDVT), 2011 IEEE International
  • Conference_Location
    Napa Valley, CA
  • ISSN
    1552-6674
  • Print_ISBN
    978-1-4577-1744-4
  • Type

    conf

  • DOI
    10.1109/HLDVT.2011.6114171
  • Filename
    6114171
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2793978