DocumentCode
2794040
Title
EEPROM Compact Model with SILC Simulation Capability
Author
Regnier, A. ; Portal, J.M. ; Aziza, H. ; Masson, P. ; Bouchakour, R. ; Relliaud, C. ; Nee, D. ; Mirabel, J.M.
Author_Institution
L2MP-Polytech - UMR CNRS 6137, IMT - Technopole de Chateau Gombert, Marseille
fYear
2006
fDate
5-8 Nov. 2006
Firstpage
26
Lastpage
30
Abstract
The objective of this paper is to present a EEPROM compact model suitable for SILC simulation. The SILC module allows simulating the retention capability of the cell after stress. Test chip array distribution and standard tunnel capacitor are used to extract the SILC module parameters. Thus the extraction procedure is detailed. The description of the complete model is presented. A simulation example is given and validated versus measurements.
Keywords
EPROM; capacitors; leakage currents; EEPROM; SILC module; compact model; standard tunnel capacitor; stress-induced leakage current; test chip array distribution; Capacitors; EPROM; Logic arrays; Nonvolatile memory; Portals; Semiconductor device measurement; Stress; Tail; Testing; Voltage; EEPROM; Model; Reliability modeling; SILC;
fLanguage
English
Publisher
ieee
Conference_Titel
Non-Volatile Memory Technology Symposium, 2006. NVMTS 2006. 7th Annual
Conference_Location
San Mateo, CA
Print_ISBN
0-7803-9738-X
Type
conf
DOI
10.1109/NVMT.2006.378870
Filename
4228429
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