Three-level converters with selective Harmonic Elimination PWM for HVDC application

Author

Beza, Mebtu ; Norrga, Staffan

Author_Institution

Dept. of Energy & Environ., Chalmers Univ. of Technol., Göteborg, Sweden

fYear

2010

fDate

12-16 Sept. 2010

Firstpage

3746

Lastpage

3753

Abstract

In a voltage source converter (VSC) based HVDC system, the modulation scheme used is an important factor in achieving a desired harmonic performance with allowable semiconductor losses. In this paper, the use of selective Harmonic Elimination Pulse Width Modulation (HEPWM) for a three-level Neutral Point Clamped (NPC) converter in VSC based HVDC application will be discussed. Steady state performance of the converter system in terms of harmonics and losses will be evaluated using MATLAB and PSCAD/EMTDC simulation. Simulation results show a 37% improvement in total semiconductor loss with better harmonic performance by using the three-level solution compared to the two-level solution with the stated modulation scheme.

Keywords

HVDC power convertors; PWM power convertors; power system CAD; HEPWM; HVDC application; MATLAB; PSCAD/EMTDC simulation; harmonic elimination pulse width modulation; semiconductor loss; three-level converters; three-level neutral point clamped converter; voltage source converter; Converters; Harmonic analysis; Insulated gate bipolar transistors; Power harmonic filters; Pulse width modulation; Semiconductor diodes; HEPWM; NPC Converter; Three-level Solution; Two-level Solution;

fLanguage

English

Publisher

ieee

Conference_Titel

Energy Conversion Congress and Exposition (ECCE), 2010 IEEE

Conference_Location

Atlanta, GA

Print_ISBN

978-1-4244-5286-6

Electronic_ISBN

978-1-4244-5287-3

Type

conf

DOI

10.1109/ECCE.2010.5617787

Filename

5617787