DocumentCode
2794591
Title
Hardware/Firmware Verification of Graphic IP
Author
Romain, Kamdem
Author_Institution
STMicroelectronics, Grenoble
fYear
2007
fDate
28-30 May 2007
Firstpage
48
Lastpage
56
Abstract
This paper describes methods and simulation techniques used to verify the functional correctness of a flexible video processing engine IP. The verification environment relies on co-simulation of the RTL IP under-design with functional building blocks, developed using SystemC constructs. We try here to assess a number of problems encountered during the verification of complex IPs such as flexibility of functions, simulation speed and performance.
Keywords
computer graphic equipment; digital signal processing chips; digital simulation; firmware; formal verification; hardware description languages; industrial property; logic CAD; program debugging; RTL IP design; SystemC construct; bug-free certification; flexible video processsor engine IP; functional correctness verification; graphic IP; hardware/firmware verification environment; simulation technique; Computer bugs; Displays; Engines; Explosions; Formal verification; Graphics; Hardware; Logic; Microprogramming; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 2007. RSP 2007. 18th IEEE/IFIP International Workshop on
Conference_Location
Porto Alegre
ISSN
1074-6005
Print_ISBN
0-7695-2834-1
Type
conf
DOI
10.1109/RSP.2007.25
Filename
4228484
Link To Document