DocumentCode
2794834
Title
Formal verification of DSP VLSI architectures: a tutorial
Author
Elleithy, Khaled M. ; Hummaigani, Muhammad A.
Author_Institution
Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
Volume
1
fYear
1994
fDate
3-5 Aug 1994
Firstpage
351
Abstract
In this tutorial paper the area of formal verification of DSP VLSI architectures is presented. The paper discuses the following topics: production systems, formal logic, the equational approach, and the signal flow graph approach. Each approach is explained using one or more of the currently available systems
Keywords
VLSI; digital signal processing chips; formal logic; formal verification; knowledge based systems; signal flow graphs; DSP VLSI architectures; equational approach; formal logic; formal verification; production systems; signal flow graph approach; Circuits; Digital signal processing; Digital signal processing chips; Formal verification; Hardware; Libraries; Production systems; Specification languages; Tutorial; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location
Lafayette, LA
Print_ISBN
0-7803-2428-5
Type
conf
DOI
10.1109/MWSCAS.1994.519255
Filename
519255
Link To Document