Power SiC DMOSFET model accounting for JFET region nonuniform current distribution

The main goal of this work is development of a new circuit-based SiC DMOSFET model which physically represents the mechanism of current saturation in power SiC DMOSFET. Finite element simulations show that current saturation for a typical device geometry is due to two-dimensional carrier distribution effects in the JFET region caused by the current spreading from the channel to the JFET region. For high drain-source voltages, most of the voltage-drop occurs in the current-spreading region located in the JFET region close to the channel.