DocumentCode :
2795068
Title :
OSCAR multi-grain architecture and its evaluation
Author :
Kasahara, H. ; Ogata, W. ; Kimura, E. ; Matsui, G. ; Matsuzaki, H. ; Okamoto, M. ; Yoshida, A. ; Honda, H.
Author_Institution :
Dept. of EECE, Waseda Univ., Tokyo, Japan
fYear :
1997
fDate :
22-24 Oct 1997
Firstpage :
106
Lastpage :
115
Abstract :
OSCAR (Optimally Scheduled Advanced Multiprocessor) was designed to efficiently realize multi-grain parallel processing using static and dynamic scheduling. It is a shared memory multiprocessor system having centralized and distributed shared memories in addition to local memory on each processor with data transfer controller for overlapping of data transfer and task processing. Also, its Fortran multigrain compiler hierarchically exploits coarse grain parallelism among loops, subroutines and basic blocks, conventional medium grain parallelism among loop-iterations in a Doall loop and near fine grain parallelism among statements. At the coarse grain parallel processing, data localization (automatic data distribution) been employed to minimize data transfer block, explicit synchronization can be removed by use of a clock level accurate code scheduling technique with architectural supports. This paper describes OSCAR´s architecture, its compiler and the performance for the multi-grain parallel processing. OSCAR´s architecture and compilation technology will be more important in future High Performance Computers and single chip multiprocessors
Keywords :
distributed memory systems; parallel architectures; performance evaluation; shared memory systems; OSCAR; Optimally Scheduled Advanced Multiprocessor; coarse grain parallelism; distributed shared memories; fine grain parallelism; medium grain parallelism; multi-grain parallel processing; shared memory multiprocessor; single chip multiprocessors; Algorithms; Automatic control; Centralized control; Computer architecture; Control systems; Dynamic scheduling; Multiprocessing systems; Parallel processing; Processor scheduling; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Innovative Architecture for Future Generation High-Performance Processors and Systems, 1997
Conference_Location :
Maui, HI
ISSN :
1537-3223
Print_ISBN :
0-8186-8424-0
Type :
conf
DOI :
10.1109/IWIA.1997.670416
Filename :
670416
Link To Document :
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