Defect-oriented test- and layout-generation for standard-cell ASIC designs

This work shows a new concept to extend the hierarchical approach of standard-cell circuit design into the area of defect-oriented test pattern generation. For this purpose test patterns to detect shorts for each standard-cell are created separately. A new defect-oriented test generator (DOT) is using these single cell test pattern lists to create test patterns for the complete circuit. Additionally, test patterns for the routing network will be created. This work targets mainly shorts, but also other defects can be treated in a similar way. In order to generate tests only for relevant combinations of shorted nodes, the critical area for both the cells and the routing network is determined separately and the probability for each short is computed. Shorts inside the routing network can show sequential behaviour. The proposed test pattern generator is also able to find tests for such kind of defects. As the effort to test sequential defects can vary from short to short, a new testability analysis is presented. Based on this analysis a redesign of the circuit layout is proposed. This "layout for testability" approach is therefore a defect oriented equivalent for "design for testability" methods.