Title :
Design and implementation of a high resolution DPWM based on a low-cost FPGA
Author :
Ge Lu-Sheng ; Chen Zong-Xiang ; Chen Zhi-Jie ; Liu Yan-Fei
Author_Institution :
Sch. of Electr. Eng. & Inf., Anhui Univ. of Technol., Ma An Shan, China
Abstract :
This paper proposes a new implementation method which can achieve DPWM with time resolution under 100ps. Utilizing the carry flag delay time, a high resolution DPWM can be achieved by low cost FPGA. The proposed DPWM method is, in principle, intended for FPGA implementation, but it can achieve high time resolution DPWMS and can be implemented in low cost FPGA. Linearity was manually optimized using the presented technique which reduces the non-linearity error. The proposed DPWM with 15-bit and 70-80ps resolution with a switching frequency of 1 MHz has been successfully implemented on a low-cost Atera Cyclone-II series FPGA.
Keywords :
PWM power convertors; field programmable gate arrays; logic design; carry flag delay time; frequency 1 MHz; high resolution DPWM; low-cost Atera Cyclone-II series FPGA; low-cost FPGA; nonlinearity error; time 70 ps to 80 ps; word length 15 bit; Adders; Clocks; Delay; Delay lines; Field programmable gate arrays; Manuals; Pulse width modulation; DPWM; FPGA; adder delay line; high resolution;
Conference_Titel :
Energy Conversion Congress and Exposition (ECCE), 2010 IEEE
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-5286-6
Electronic_ISBN :
978-1-4244-5287-3
DOI :
10.1109/ECCE.2010.5617866
