Reconfigurable parallel approximate string matching on FPGAs

This paper presents a design and implementation of a reconfigurable parallel approximate string matching hardware on FPGAs. The design is based on a linear systolic dataflow algorithm, and control logic is added to reconfigure the resulting hardware. For the k-differences version of the approximate string matching problem, the proposed approach finds all approximate occurrences of a pattern in the reference string, with the time complexity O(n+m) where n and m are lengths of the reference string and the pattern, respectively. Unlike other hardware approaches found in the literature, the design is size optimized since it uses only m PEs that are independent on the reference string length. Also the design is flexible for handling arbitrary size pattern strings within the maximum bound. The design is implemented and tested on the target device Xilinx Spartan 2S XC2S200EPQ208.