Massively parallel hardware architecture for genetic algorithms

In this paper, we propose a massively parallel architecture for hardware implementation of genetic algorithms. This is design is quite innovative as it provides a viable solution to the fitness computation problem, which depends heavily on the problem-specific knowledge. The proposed architecture is completely independent of such specifics. It implements the fitness computation using a neural network. The hardware implementation of the used neural network is stochastic and thus minimise the required hardware area without much increase in response time. Finally, we compare the proposed hardware and existing ones.