DocumentCode :
2795953
Title :
Java to hardware compilation for non data flow applications
Author :
Andersson, Per ; Kuchcinski, Krzysztof
Author_Institution :
Lund Univ., Sweden
fYear :
2005
fDate :
30 Aug.-3 Sept. 2005
Firstpage :
330
Lastpage :
337
Abstract :
Java has proven to be a powerful language for software development. In this paper we show that it is also suitable for hardware compilation, making it an attractive language for embedded system development. Our compilation technique, which is presented here, is based on separating different aspects of the program and use dedicated and specialised optimisations and code generators for each aspect. In this paper we focus on efficient implementation of random memory accesses, i.e. reference intensive tasks, such as graph traversal. We show that for these tasks the hardware generated by our compiler is up to 1.8 times faster than a software implementation. We also show how recursive algorithms can be mapped to hardware using our tool.
Keywords :
Java; data flow graphs; embedded systems; hardware-software codesign; program compilers; Java language; code generators; embedded system development; graph traversal; hardware compilation; nondata flow application; optimisation; random memory access; recursive algorithm; reference intensive tasks; software development; Application software; Data structures; Embedded system; Field programmable gate arrays; Flow graphs; Hardware; Java; Productivity; Programming; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design, 2005. Proceedings. 8th Euromicro Conference on
Print_ISBN :
0-7695-2433-8
Type :
conf
DOI :
10.1109/DSD.2005.53
Filename :
1559822
Link To Document :
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