Chip Power Interconnection

Author

Novotny, M. ; Jankovsky, J. ; Szendiuch, I.

Author_Institution

Brno Univ. of Technol., Brno

fYear

2007

fDate

9-13 May 2007

Firstpage

183

Lastpage

186

Abstract

This paper describes recent developments made to the finite element modeling of wire bonding interconnection, extending its capability to handle viscoplastic behavior. In this project a test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards will be developed and realised. Especially the reliability of interconnections of semiconductor chips under high current regime until 10 A, or more, is emphasised. This study discusses the analysis methodologies as implemented in the ANSYS finite element simulation software tool. The aim of this paper is to improve reliability of chip interconnection and to increase durability of these structures.

Keywords

finite element analysis; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; lead bonding; printed circuits; stress analysis; viscoplasticity; ANSYS finite element simulation software tool; chip power interconnection; finite element modeling; integrated circuit interconnection reliability; printed circuit boards; semiconductor chips; test system; viscoplastic behavior; Bonding; Circuit testing; Finite element methods; Integrated circuit interconnections; Integrated circuit reliability; Integrated circuit testing; Power system interconnection; Power system modeling; System testing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Technology, 30th International Spring Seminar on

Conference_Location

Cluj-Napoca

Print_ISBN

987-1-4244-1218-1

Electronic_ISBN

987-1-4244-1218-1

Type

conf

DOI

10.1109/ISSE.2007.4432844

Filename

4432844