Title :
Using a tightly-coupled pipeline in dynamically reconfigurable platform FPGAs
Author :
Silva, Miguel L. ; Ferreira, João Canas
Author_Institution :
FEUP, Porto, Portugal
fDate :
30 Aug.-3 Sept. 2005
Abstract :
The paper describes the organization and use of a pipeline that is tightly-coupled to the CPU inside a platform FPGA with support for dynamic partial reconfiguration. It describes the overall hardware system organization and the pipeline structure, and presents the associated development environment and run-time support system, including the support for dynamically changing pipeline implementations and altering the operations of a pipeline stage.
Keywords :
field programmable gate arrays; pipeline processing; reconfigurable architectures; associated development environment; dynamic partial reconfiguration; hardware system organization; pipeline implementation; platform FPGA; run-time support system; tightly-coupled pipeline structure; Counting circuits; Digital systems; Fabrics; Field programmable gate arrays; Logic arrays; Pattern matching; Pipelines; Reconfigurable logic; Runtime; Switches;
Conference_Titel :
Digital System Design, 2005. Proceedings. 8th Euromicro Conference on
Print_ISBN :
0-7695-2433-8
DOI :
10.1109/DSD.2005.74
