Hardware implementation of Recurrent S_CMAC_GBF based on FPGA

This study is to design and develop the hardware structure of recurrent S-CMAC_GBF (Ching-Tsan Chiang et al., 2004), and to implement and test the hardware structure by using FPGA chip. S_CMAC_GBF has the same learning convergence characteristic as in CMAC_GBF, but with stronger system accuracy. The learning structure of recurrent enables S_CMAC_GBF with the ability to solve dynamic system or time relevant problem. Although S_CMAC_GBF and recurrent S_CMAC_GBF have outstanding learning performances and applications in static and dynamic systems, both are restricted to the huge computer size and input/output speed, therefore, it is hard to expand their applications. This study reduces the system size to IC grade and increase the processing speed from m sec to mu sec. And there are two temporal relevant examples are employed to demonstrate the performance of the hardware implementation.