Title :
Performance and side-channel attack analysis of a self synchronous montgomery multiplier processing element for RSA in 40nm CMOS
Author :
Devlin, Benjamin ; Ueki, Hiroshi ; Mori, Shinsuke ; Miyauchi, Shoko ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
Dept. of Electron. Eng., Univ. of Tokyo, Tokyo, Japan
Abstract :
We propose a Montgomery multiplier composed of gate-level self synchronous processing elements (SS-PE) that can be used to create scalable-length modular multipliers with no broadcast signals for high throughput. A 40nm test circuit shows the SS-PE operates from 0.4V to 1.3V at 20°C without tuning, with 2.1 Gb/s data-throughput, 476ps delay at 1.1V, and energy per operation of 322fJ/op at 1.1V and 1.40fJ/op with voltage scaling to 0.4V. A 8-bit RSA is implemented using SS-PEs, and shows 186Mb/s and 130ns data-throughput and time respectively for the average case of decryption. Side-channel attacks using simple power analysis, differential power analysis, and high order differential power analysis show secure operation with no information leakage after 50,000 measurements.
Keywords :
CMOS integrated circuits; multiplying circuits; power aware computing; CMOS integrated circuit; RSA; Rivest-Shamir-Adleman; SS-PE; bit rate 186 Mbit/s; bit rate 2.1 Gbit/s; gate-level self synchronous processing elements; high order differential power analysis; scalable-length modular multipliers; self synchronous Montgomery multiplier processing element; side-channel attack analysis; simple power analysis; size 40 nm; temperature 20 degC; time 130 ns; time 476 ps; voltage 0.4 V to 1.3 V; voltage scaling; word length 8 bit;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
Conference_Location :
Kobe
DOI :
10.1109/ASSCC.2012.6570807
