Title :
CSPL: a capacitor-separated pass-transistor logic
Author :
Yamashita, Takahiro ; Asada, Kunihiro
Author_Institution :
Fac. of Eng., Tokyo Univ., Japan
Abstract :
In this study, a method for reducing delay time in a pass-transistor circuit is proposed, where capacitor and latching sense amplifier for pass-transistor logic are used. The coupling capacitor realizes the setting of the optimum bias and supply voltage in each pass-transistor and sense amp. We show the circuit operated 9.5 times as fast as the conventional CMOS circuits for typical applications at 1.2 V
Keywords :
CMOS logic circuits; delays; high-speed integrated circuits; low-power electronics; 1.2 V; CSPL; LV operation; capacitor-separated pass-transistor logic; coupling capacitor; delay time; latching sense amplifier; optimum bias setting; pass-transistor circuit; supply voltage; CMOS logic circuits; Capacitance; Capacitors; Clocks; Delay effects; Logic circuits; Pulse inverters; Switches; Synthetic aperture sonar; Voltage;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896900
