Title :
CMOS capacitor coupling logic (C3L) circuits
Author :
Huang, Hong-Yi ; Wang, Teng-Neng
Author_Institution :
Dept. of Electron. Eng., Fu-Jen Univ., Taiwan
Abstract :
The multi-valued logic has been drawing considerable attention as a promising candidate for building future integrated circuits. The capacitor coupling technique is one of the effective methods to approach the performance issue. In this paper the capacitor coupling logic (C3L) circuit to implement CMOS logic gates is proposed. The multiple inputs NAND, NOR, AOI, and OAI gates can be easily realized using the technique. Furthermore, the carry and sum circuit of a full-adder is designed and verified
Keywords :
CMOS logic circuits; adders; integrated circuit design; logic design; logic gates; multivalued logic; multivalued logic circuits; AOI gates; CMOS capacitor coupling logic circuits; CMOS logic gates; NAND gates; NOR gates; OAI gates; carry/sum circuit; full-adder; integrated circuits; multi-valued logic; multiple input gates; Arithmetic; CMOS logic circuits; Capacitors; Coupling circuits; Engineering drawings; Logic circuits; Multivalued logic; Page description languages; Parasitic capacitance; Voltage;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896901
