DocumentCode
2796757
Title
8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparator
Author
Terada, J. ; Matsuya, Y. ; Morisawa, F. ; Kado, Y.
Author_Institution
NTT Telecommun. Energy Labs., Kanagawa, Japan
fYear
2000
fDate
2000
Firstpage
53
Lastpage
56
Abstract
A very low-power, high-speed flash A/D converter front-end composed of a new transconductance latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at 1 V and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW
Keywords
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); high-speed integrated circuits; low-power electronics; 1 V; 6 bit; 8 mW; A/D converter; A/D front-end; butterfly sorting technique; convertor monotonicity; dynamic range; high-speed flash ADC; low-power ADC; power consumption; transconductance latched comparator; Circuits; Clocks; Energy consumption; Frequency; Inverters; Latches; Low voltage; Sampling methods; Timing; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location
Cheju
Print_ISBN
0-7803-6470-8
Type
conf
DOI
10.1109/APASIC.2000.896906
Filename
896906
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