Title :
A differential type CMOS phase frequency detector
Author :
Chang, Robert C. ; Kuo, Lung-Chih
Author_Institution :
Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan
Abstract :
We propose a new differential-type CMOS phase frequency detector for a PLL design. The circuit uses two D-FFs and two delay buffers. Besides, it adopts two reset functions R1 and R2 to avoid the UP and DN being logic-1 simultaneously. Thus, any mismatch current of the charge pump circuit will not affect the performance of the PLL. The detector can greatly reduce the dead-zone phenomenon in the phase characteristic, which is important in low-jitter applications. In order to detect the smallest phase error the new detector employs delay buffers to shift the phase error. The circuit is simulated by HSPICE with the 0.35 μm CMOS technology
Keywords :
CMOS digital integrated circuits; CMOS integrated circuits; SPICE; buffer storage; circuit simulation; delay circuits; differential detection; phase detectors; phase locked loops; 0.35 mum; CMOS phase frequency detector; CMOS technology; HSPICE; PLL design; charge pump circuit; circuit simulation; dead-zone phenomenon; delay buffers; differential-type detector; low-jitter applications; mismatch current; phase characteristic; phase error detection; reset functions; CMOS technology; Charge pumps; Circuit simulation; Delay; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Virtual colonoscopy; Voltage;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896908
