DocumentCode
2796804
Title
Adaptive AC/DC output buffer with reduced ground bounce and output ringing
Author
Jou, Shyh-Jye ; Kuo, Shu-Hua ; Chiu, Jui-Ta ; Lin, Victor
Author_Institution
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
fYear
2000
fDate
2000
Firstpage
65
Lastpage
68
Abstract
A CMOS output buffer with AC and DC stages and adaptively feedback control scheme is proposed. Implementation results show that it can reduce the output ring by 60%, power/GND line bounce by 40% for the case of 2 ns rise and fall time with 40 pF output loading
Keywords
CMOS analogue integrated circuits; buffer circuits; circuit feedback; integrated circuit noise; 2 ns; 40 pF; CMOS AC/DC output buffer; adaptive feedback control; output ringing; power/ground line bounce; simultaneous switching noise; Delay effects; Frequency; Inductance; Integrated circuit noise; MOS devices; Noise generators; RLC circuits; Signal design; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location
Cheju
Print_ISBN
0-7803-6470-8
Type
conf
DOI
10.1109/APASIC.2000.896909
Filename
896909
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