Title :
Design of high speed CMOS prescaler
Author :
Hwang, Myung-Woon ; Hwang, Jong-Tae ; Cho, Gyu-Hyeong
Author_Institution :
Circuit & Syst. Lab., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Abstract :
A high-speed divide-by-2 prescaler is designed in a 0.8 um CMOS. New ECL-like D flip-flop is proposed having source-folded diode clamping. Significant amount of speed up can be obtained using source-folded diode with proper sizing ratio of transistors, and lower power consumption can be obtained by designing low power D flip-flop and removing additional input-amplifying buffer. The simulated maximum input frequency of the suggested prescaler reaches up to 3.15 GHz with only 5 mA and 1.8 GHz with 1.6 mA at 3.3 V
Keywords :
CMOS logic circuits; emitter-coupled logic; flip-flops; high-speed integrated circuits; low-power electronics; prescalers; 0.8 micron; 1.8 GHz; 3.15 GHz; 3.3 V; 5 mA; CMOS prescaler; D flip-flop; ECL; high-speed design; low-power circuit; source-folded diode clamping; CMOS technology; Circuits; Costs; Diodes; Energy consumption; Flip-flops; Frequency synthesizers; Modems; Radio frequency; Voltage-controlled oscillators;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896915
