• DocumentCode
    2796994
  • Title

    RING-DATA ORDER: A new cache coherence protocol for ring-based multicores

  • Author

    Jin Young Park ; Choi, Lynn

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Korea Univ., South Korea
  • fYear
    2009
  • fDate
    21-24 June 2009
  • Firstpage
    82
  • Lastpage
    88
  • Abstract
    Ring-data order mechanism is motivated to solve cache coherence ordering for ring-based multicores. For point to point ring interconnects, the existing ordering-point mechanism is known for poor average performance due to its long response latency. Greedy-order mechanism is simple but the performance is still unacceptable because the requester should often retry to complete a coherent operation. Ring-order mechanism is the best known algorithm so far but special storage and management overhead are expected due to its token management. This paper proposes a new mechanism called ring-data order which is as simple as greedy-order but more efficient than ring-order. Ring-data order determines the order by data transfer sequence. The unbounded retries of greedy-order can be eliminated by blocking incoming coherence request which contains data. Blocked request restarts to traverse the ring interconnect when the coherence operation for current node is completed. Blocking is also used in ring-order mechanism. But ring-data order also eliminates token and its additional management overhead without sacrificing performance. Using a custom-built multicore simulator with profiled SPEC 2000 integer benchmark suites we demonstrate that ring-data order can achieve the same level of performance as ring-order without the overhead of token management.
  • Keywords
    cache storage; greedy algorithms; multiprocessing systems; parallel processing; semiconductor technology; SPEC 2000; cache coherence protocol; custom built multicore simulator; data transfer sequence; greedy order mechanism; ordering point mechanism; point to point ring interconnect; ring based multicore; ring data order mechanism; token management; Bandwidth; Costs; Delay; Energy consumption; Frequency; Multicore processing; Protocols; Silicon; Transmission lines; Cache; Coherence; Multicore; Ordering;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing & Simulation, 2009. HPCS '09. International Conference on
  • Conference_Location
    Leipzig
  • Print_ISBN
    978-1-4244-4906-4
  • Electronic_ISBN
    978-1-4244-4907-1
  • Type

    conf

  • DOI
    10.1109/HPCSIM.2009.5192668
  • Filename
    5192668