A novel rotational VLSI architecture based on extended elementary angle set CORDIC algorithm

The CORDIC algorithm is a well-known iterative method for the computation of vector rotation. For applications that require forward rotation (or vector rotation) only, the angle recoding (AR) technique provides a relaxed approach to speed up the operation of the CORDIC algorithm. In this paper, we further apply the concept of the AR technique to extend the elementary angle set in the micro-rotation phase. This technique is called the Extended Elementary-Angle Set (EEAS) scheme. The proposed EEAS scheme provides a more flexible way of decomposing the target rotation angle in CORDIC operation, and its quantization error performance is better than the AR technique. Meanwhile, we also propose an improved scaling operation, called Extended Type-II (ET-II) scaling operation, as the scaling scheme for the EEAS-based CORDIC algorithm. With the aid of the proposed EEAS scheme and ET-II scaling operation, we require only 39% iterations number in the iterative CORDIC structure, or use 39% hardware complexity in the parallel CORDIC structure compared with the conventional CORDIC approach. Hence, low-power/high-speed CORDIC VLSI architectures become feasible without sacrificing SQNR performance