Title :
Functional cache simulator for multicore
Author :
Ratanaworabhan, Paruj
Author_Institution :
Dept. of Comput. Eng., Kasetsart Univ., Bangkok, Thailand
Abstract :
This paper presents the design and construction of a light-weight execution-driven cache simulator for multicore CPU. We implement the simulator as a Pin tool, running on top of Pin, a dynamic instrumentation tool developed by Intel. We then use it to study the cache behavior of 13 multithreaded programs selected from the two well-recognized benchmark suites, SPLASH2 and PARSEC. We plan to release the tool as open-source software and hope that the computer architecture research community would benefit from it.
Keywords :
cache storage; computer architecture; digital simulation; multi-threading; multiprocessing systems; public domain software; Intel; PARSEC; Pin tool; SPLASH2; computer architecture research community; dynamic instrumentation tool; execution-driven cache simulator; functional cache simulator; multicore CPU; multithreaded programs; open-source software; Benchmark testing; Coherence; Multicore processing; Oceans; Protocols; Software;
Conference_Titel :
Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2012 9th International Conference on
Conference_Location :
Phetchaburi
Print_ISBN :
978-1-4673-2026-9
DOI :
10.1109/ECTICon.2012.6254278
