Title :
VLSI processor of parallel genetic algorithm
Author :
Choi, Yun-Ho ; Chung, Duck Jin
Author_Institution :
Sch. of Electr. & Comput. Eng., Inha Univ., Inchon, South Korea
Abstract :
In this paper, we proposed a hardware-oriented parallel genetic algorithm processor (GAP). It is a more efficient parallel GAP based on the steady-state GA with modified tournament selection. In addition, our design was applied to the parallelisms of coarse-grain and fine-grain for parallel and distributed processing in the pursuit of even better performance than the single GAP. In this paper, the proposed parallel GAP is implemented on the PCIGEN10K board with two EFP10K100A240-1 devices. The proposed parallel GAP (2-processor) increased the speed of finding the optimal solution by about 50% more than the single GAP
Keywords :
VLSI; genetic algorithms; microprocessor chips; parallel architectures; EFP10K100A240-1 devices; PCIGEN10K board; VLSI; coarse-grain; distributed processing; fine-grain; hardware-oriented parallel genetic algorithm processor; modified tournament selection; steady-state GA; Biological cells; Concurrent computing; Distributed processing; Genetic algorithms; Genetic engineering; Hardware; Parallel processing; Software algorithms; Steady-state; Very large scale integration;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896929
