DocumentCode :
2797212
Title :
Static-based verification of memory BIST integration
Author :
Lee, Kab Joo J ; Kim, Seunghan ; Park, Shihyeon ; Yoo, Youngdoo
Author_Institution :
ASIC Div., Samsung Electron. Co. Ltd., Kyungki-Do, South Korea
fYear :
2000
fDate :
2000
Firstpage :
151
Lastpage :
154
Abstract :
Static-based verification methodologies are employed to minimize iterative simulations due to functional and timing problems after BIST integration into an ASIC. Formal equivalence checking is used to verify if BIST signals are correctly integrated into an ASIC. Static Timing Analysis (STA) is used to verify BIST timing. Two ASICs, implemented using 0.25 μm technology, are used to apply static-based verification methodologies. Our experimental results show that static-based verification achieves significant verification speedup compared to simulation. This allows fast and early detection of function and timing errors that may be introduced during BIST integration:
Keywords :
application specific integrated circuits; built-in self test; integrated circuit testing; iterative methods; logic testing; timing; 0.25 micron; ASIC; formal equivalence checking; iterative simulations; memory BIST integration; static timing analysis; static-based verification methodologies; timing errors; timing problems; verification speedup; Application specific integrated circuits; Automatic control; Built-in self-test; Controllability; Design optimization; Iterative methods; Large scale integration; Logic design; Logic testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
Type :
conf
DOI :
10.1109/APASIC.2000.896931
Filename :
896931
Link To Document :
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