Asynchronous implementation of 1024-bit modular processor for RSA cryptosystem

Author

Kim, Young Sae ; Kang, Woo Seok ; Choi, Jun Rim

Author_Institution

Sch. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Taegu, South Korea

fYear

2000

fDate

2000

Firstpage

187

Lastpage

190

Abstract

In this paper, an implementation method to optimize a 1024-bit RSA processor is presented. Basically, the Montgomery algorithm is used and modified considering the large bit modular multiplication. We propose a new architecture for 1024-bit RSA processing in order to reduce the required hardware resources. The new architecture is also fit for an effective I/O interface. We have implemented a single-chip 1024-bit RSA processor based on the modified algorithm and architecture with 0.65-μm SOG technology using Verilog HDL. As a result, it is shown that the processor can perform 1024-bit RSA operation in less than 43 ms at 50 MHz

Keywords

application specific integrated circuits; asynchronous circuits; digital arithmetic; digital signal processing chips; high-speed integrated circuits; public key cryptography; 0.65 micron; 1024 bit; 43 ms; 50 MHz; ASIC; I/O interface; Montgomery algorithm; RSA cryptosystem; RSA processing; SOG technology; Verilog HDL; asynchronous implementation; large bit modular multiplication; modified modular exponentiation; modular processor; single-chip RSA processor; Algorithm design and analysis; Data communication; Data security; Electronic commerce; Hardware design languages; Optimization methods; Public key; Public key cryptography; System performance; Web and internet services;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896940

Filename

896940