Asynchronous implementation of modular exponentiation for RSA cryptography

Author

Shieh, Ming-Der ; Wu, Chien-Hsing ; Sheu, Ming-hwa ; Sheu, Jia-Lin ; Wu, Che-Han

Author_Institution

Dept. of Electron. Eng, Nat. Yunlin Univ. of Sci. & Technol., Taiwan

fYear

2000

fDate

2000

Firstpage

191

Lastpage

194

Abstract

This paper presents an efficient VLSI implementation of the modular exponentiation, commonly used in RSA cryptography, based on the asynchronous behavior of the modular multiplication. The basic idea is to partition the operand (multiplier) into several equal-sized segments and then to perform the multiplication and residue calculation of each segment in a micropipelining fashion. Experimental results show that on the average, more than 20% operations can be saved by taking into account the asynchronous behavior of the modular multiplication. The resulting implementation has the characteristics of modular design, simple control, expandable structure, and the critical path is independent of the size of the modulus

Keywords

VLSI; asynchronous circuits; computer architecture; digital signal processing chips; distributed algorithms; multiplying circuits; performance evaluation; pipeline arithmetic; public key cryptography; RSA cryptography; VLSI implementation; asynchronous implementation; expandable structure; micropipelining fashion; modular exponentiation; modular multiplication; residue calculation; Algorithm design and analysis; Application software; Communication system control; Data communication; Data security; Hardware; Paper technology; Partitioning algorithms; Public key cryptography; Size control;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896941

Filename

896941