Title :
SYSTAT: a system level timing verifier
Author :
Hojat, Shervin ; Bonyadi, Mehdi ; Yong, Suksoon ; Bonyadi, Shohreh
Author_Institution :
NCR Corp., San Diego, CA, USA
Abstract :
Timing verification is one of the most critical steps in the design of digital systems to ensure that the system functions correctly at an expected speed. SYSTAT (SYStem level Timing Analysis Tool) is a static timing verification tool which was developed to address the advanced needs and requirements of engineers at NCR E&M San Diego. An overview is presented of some of the advanced algorithms and techniques used within SYSTAT. Features that are being added to SYSTAT are summarized
Keywords :
circuit analysis computing; delays; logic CAD; SYSTAT; digital systems; static timing verification tool; system level timing verifier; Analytical models; Application specific integrated circuits; CMOS technology; Circuit analysis; Circuit simulation; Circuit testing; Computer errors; National electric code; Pattern analysis; Timing;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140718
